"지능형 반도체 생태계 구축을 위한 아날로그 회로의 자동생성" Byungsub Kim,

IITP Tech & Future Insight Concert, 2019

"A Feed Forward Equalized Transmitter Architecture, which is Robust to Coefficient Errors, for High-Speed Wireline Communication" Byungsub Kim, Seungho Han, Sooeun Lee, Minsoo Choi, Jae-Yoon Sim, and Hong-June Park,

IEEE IMS/RFIC Workshop On Digital Pre-Distortion and Post-Correction from DC to mmWave for Wireline and Optical Communication, 2018

"A Theory and Practice To Overcome 50-Ω Legacy in High-Speed Link Applications" Byungsub Kim,

IEEE International SoC Design Conference, 2017

"An Integrated Potentiostat" Puneet Kanwar Kaur , Sooeun Lee and Byungsub Kim,

IDEC SoC Congress Chip Design Contest, 2017

"A Coefficient-Error-Robust FFE TX with 230% Eye Variation Improvement Without Calibration in 65-nm CMOS Technology" Byungsub Kim,

IEEE CAS Society Korean Workshop on Circuits and Systems, 2017

"Hierarchical Design Automation for Electronics" Byungsub Kim,

EDA Summer Workshop, 2015

"An Energy-Efficient Equalized Transceiver for RC-dominant Channels" Byungsub Kim,

POSTECH-NTU Silicon Interposer Workshop, 2015

"DFE-IIR Equalization" Byungsub Kim,

POSTECH-NTU Silicon Interposer Workshop, 2015

"Revisiting High-Speed Interconnect Channel Modeling" Byungsub Kim,

nce The 11th International System-on-Chip (SoC) Conference, 2013

"Design Automation Techniques for High-Speed Interconnects" Byungsub Kim,

CMOS Emerging Technology, 2013

"실리콘 인터포저 연구동향" Byungsub Kim,

SoC 학술대회, 2012

"Future State-of-the-Art Electrical Interconnect" Byungsub Kim and Vladimir Stojanovic,

Workshop on the Interaction between Nanophotonic Devices and Systems (co-located with the 43rd Annual IEEE ACM International Symposium on Microarchitecture), 2010