KR101539816B1 - Fractional - rate decision feedback equalization - Google Patents

Abstract

A 1 / n-rate decision feedback equalizer (DFE) and method includes a number of branches. Each of the branches includes a summer circuit configured to add a feedback signal to the received input and includes a latch configured to receive an output of the summer circuit according to a clock signal. The feedback circuit includes a multiplexer and a filter, the multiplexer being configured to receive as an input the output of each branch, having a clocked selection input, and each branch And the filter is configured to remove intersymbol interference (ISI) from the received input to be provided to the summing circuit of each branch.

Description

[0001] FRACTIONAL - RATE DECISION FEEDBACK EQUALIZATION [0002] FIELD OF THE INVENTION [0003]

The present invention generally relates to equalization techniques for high-speed data transmission, and more particularly to implementations and methods of decision feedback equalizer circuits for high-speed data communication with improved power efficiency.

As the advances in technology increase the processing power of digital computing engines and as interconnected networks are increasingly being exploited to take advantage of the processing power, higher bandwidth data transfers are required for systems, ≪ / RTI > communication routers. In serial communications, raising data rates to more than a few gigabits per second is hampered by limited channel bandwidth. The bandwidth of an electrical channel (e.g., transmission line) can be reduced due to some physical effects, which include reflections due to skin effect, dielectric loss, and impedance discontinuity. In the time domain, the limited channel bandwidth leads to broadening of transmitted pulses over more than one unit interval (UI), resulting in a received signal having an inter-symbol interference (ISI) Interference.

An effective way to compensate for signal distortions due to limited channel bandwidth is to add equalization functions to the input / output (I / O) circuitry. The use of a nonlinear equalizer known as a crystal-feedback equalizer (DFE) in a receiver is particularly suitable for equalizing high-loss channels. Unlike linear equalizers, the DFE can flatten the channel response (and also reduce signal distortion) without amplifying noise or crosstalk. This is an important advantage when the channel loss exceeds 20-30 dB.

In Fig. 1, a conventional multi-tap DFE 10 is shown. The binary output of a decision-making slicer (or latch) 12 is captured within a shift register delay line formed from successive latches 14. [ Previously stored in the shift register (14) (previously) determined bits are fed back with the weighted tap coefficient (weighted tap-coefficients) (H1 , H2, ..., H n), then summing amplifier (or groups combined) Is summed with the input signal received by the antenna 16. When the sizes and polarities of the tap weights (H1, H2, etc.) are appropriately adjusted to match the channel characteristics, the ISI ("post-cursor"quot; cursor ISI ") does not occur, and therefore the bits can be detected by the slicer 12 with a low bit error rate (BER). The tap weighting factors may be adjusted manually or automatically through an appropriate adaptive algorithm.

In general, the more taps that can be used to remove the ISI, the more efficient equalization may occur. Practical DFE implementations often employ ten (10) feedback taps to equalize electrical channels that are difficult to operate at multi-gigabit data rates per second. However, the many latches and feedback circuits used in multi-tap DFEs consume significant power and chip area. For example, in some applications, such as a high-end processor chip with thousands of I / Os, I / O circuits consume most of the system power and chip area cost, The power and chip area costs of the multi-tap DFE have grown exponentially, making them difficult to use.

Dense, fine-pitch silicon packaging that is expected to support tens of thousands of high data rate I / Os for local chip-to-chip interconnects. packaging technologies, the chip area and power requirements of I / O circuits will become even more stringent. One example of such high density packaging techniques is a silicon carrier, the basic concept of which is shown in Fig.

In Fig. 2, two chips 20 and 22 are mounted on the silicon carrier 24 and connected to each other by a surface wiring 26. The pitch of the surface wiring 26, fabricated in a standard CMOS back-end-of-line (BEOL) process, is only a few microns so that a high density array of silicon carrier links Lt; RTI ID = 0.0 > 20 and 22. < / RTI >

Silicon through vias 28 are used to connect power and signals vertically between chips 20 and 22 and conventional primary packaging. Due to their small size, surface wirings 26 forming silicon carrier links exhibit significant resistance per unit length.

The 1 / n-rate decision feedback equalizer (DFE) includes a number of branches. Each branch includes a summer circuit configured to add a feedback signal to the received input, and each branch also includes a latch configured to receive the output of the summer circuit according to a clock signal. The feedback circuit includes a multiplexer and a filter that receives the output of each branch as an input and has a clocked select input and is coupled to a respective one of the plurality of branches to assemble a full-rate bit sequence. Branch and the filter is configured to remove intersymbol interference (ISI) from the received input provided to the summing circuit of each branch.

The decision feedback equalization method includes: providing a 1 / n-rate decision feedback equalization circuit having a plurality of branches; Summing a feedback signal from the one or more branches with the received input using a summer circuit; Receiving an output of the summer circuit in a latch in accordance with a clock signal; Feedback the output of the latch to a multiplexer, the multiplexer being configured to receive as inputs the outputs of each branch and to multiplex outputs of each branch to assemble a full-rate bit sequence; And removing an inter-symbol interference (ISI) from the received input using a continuous-time infinite impulse response (IIR) filter having a frequency-domain transfer function .

The combined slicer and summer circuit includes differential output lines, the differential output lines being connected to a plurality of differential currents to be summed. The resettable current-comparator load is coupled directly to the differential output lines and is configured to receive the summed differential currents directly from the differential output lines so that either a positive or negative differential voltage, depending on the sign of the summed differential currents, Between the differential output lines, binary 0 or 1 is latched.

A double regenerating latch includes two cascaded differential regenerating latch stages to achieve improved speed and sensitivity. The stages include a first stage and a second stage, the first stage having first input transistors of a first type, cross-coupled load transistors of a second type and reset transistors of a second type, The stage has a second type of second input transistors and a first type of cross-coupled load transistors. Thus, when the first stage is in an opaque state, i. E. When the reset transistors precharge the outputs of the first stage to the power supply voltage, the second input transistors of the second stage Lt; RTI ID = 0.0 > a < / RTI > When the first stage is activated, the first and second types of cross-coupled load transistors begin to regenerate the input signal while at the same time the output common-mode of the first stage falls fall turn on the second input transistors of the second stage. The second stage includes cross-coupled load transistors of the first type such that the output of the first stage is switched after reaching a threshold signal level that provides additional regeneration gain.

These and other features and advantages of the present invention will be apparent from the following detailed description, and the detailed description is given with reference to the accompanying drawings.

The contents of the present invention will be described in detail in the description of the preferred embodiments described below with reference to the accompanying drawings.
1 is a block diagram illustrating a conventional multi-tap DFE having tap weights adjusted to match post-cursors of a channel response.
Figure 2 is a perspective view showing a silicon carrier having two chips connected by carrier links.
Figures 3a and 3b show the characteristics of a 20 mm long silicon carrier channel, where Figure 3a shows the S21 response to frequency and Figure 3b shows the impulse response to time.
4 shows a block diagram of a DFE with an analog continuous-time IIR filter in the feedback path.
Figure 5 shows a block diagram of a DFE with both conventional discrete taps and IIR filters in the feedback path.
6 is a block diagram illustrating a half-rate DFE structure with IIR filters in one exemplary embodiment.
FIG. 7 is a timing diagram of the half-rate DFE structure shown in FIG.
Figure 8 is a schematic diagram illustrating a circuit implementation in which 2: 1 MUX and IIR filters are combined in a single stage.
9 is a schematic diagram showing an implementation of a current mode logic (CML) circuit of a DFE summing amplifier and a slicer according to the prior art.
10 is a schematic diagram illustrating a DFE current sumer and decision slicer coupled into a single stage in accordance with one embodiment.
11 is a block diagram illustrating a half-rate DFE structure with IIR filters in another embodiment employing a combined summing / slicer circuit in FIG.
12 is a schematic diagram illustrating a double regenerating latch according to one embodiment.
Figure 13 shows the measured values of the BER bathtub curves equalized by the half-rate DFE with the frequency responses of the 30 ", 40 ", and 50 " PCB channels and the IIR according to the principles of the present invention Respectively.

The present invention provides decision feedback equalizer (DFE) circuits and methods employing a filter that replaces one or more feedback loops employed to remove ISI from channels. In one embodiment, a 1 / n-rate DFE (e.g., 1 / 2- rate, 1/4-rate, etc.) (i.e., n> 1) filters the feedback signal and sends it to the summing amplifier Lt; RTI ID = 0.0 > (IIR) < / RTI > In addition, a combined summer / slicer circuit is provided, which helps to further reduce chip area and energy consumption. Dual playback latches are also provided.

Embodiments of the present invention may take the form of an entirely hardware embodiment, a complete software embodiment, or an embodiment that includes both hardware and software elements. In a preferred embodiment, the present invention is implemented in software, including, but not limited to, firmware, resident software, microcode, and the like.

In addition, the invention may take the form of a computer program product accessible from a computer usable or computer readable medium providing program code for use by or by a computer or any execution instruction system. For the purposes of this description, a computer-usable or computer readable medium may be any apparatus capable of containing, storing, communicating, communicating, or transmitting a program by or in execution instruction system, apparatus, or device. The medium may be an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system (or device or device). Examples of computer-readable media include semiconductor or semiconductor memory, magnetic tape, removable computer diskettes, random access memory (RAM), read only memory (ROM), rigid magnetic disks and optical disks . Current examples of optical disks include compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and DVD.

A data processing system for storing and / or executing program code will include at least one processor coupled directly or indirectly to memory elements via a system bus.

The memory elements include local memory, bulk storage, and cache memories employed during the actual execution of the program code, wherein the cache memories store the number of times the program code must be retrieved from the bulk storage during the actual execution of the program code times to provide a temporary storage of at least some program code. Input / output or I / O devices (including but not limited to keyboards, displays, pointing devices, etc.) may be coupled to the system directly or through intervening I / O controllers.

Network adapters may also be connected to the system via a private or public network intervening to couple data processing systems or remote printers or storage devices with other data processing systems. Modems, cable modems, and ethernet cards are the types available with current network adapters.

The circuits described herein may be part of a design for an integrated circuit chip. The chip design may be generated in a computer programming language for graphics and then stored in a computer storage medium (e.g., a disk, tape, physical hard drive, or virtual hard drive, such as within a storage access network) . If a designer does not manufacture chips or does not manufacture photolithographic masks that are used to fabricate the chip, the designer can design the resulting design to the chip manufacturer or mask manufacturers by physical means (e.g., (E.g., by providing a copy of the storage medium to be stored) or electronically (e.g., via the Internet). The stored design is then converted into a form suitable for manufacturing photolithographic masks (e.g., Graphics Data System II (GDS II)). The masks typically comprise a plurality of copies of the chip design to be formed on the wafer. Photolithographic masks are used to define certain areas of the wafer (and / or layers thereon) that are to be etched or otherwise treated.

The fabricated integrated circuit chips may be fabricated into bare die either in an untreated wafer form (i. E. As a single wafer with a plurality of unpackaged chips) or in a packaged form to the manufacturer Lt; / RTI > In the latter case, the chip may be mounted (mounted) on a single chip package (e.g., a plastic carrier, which carrier has leads attached to a motherboard or other higher level carrier) ) Or a multi-chip package (e.g., a ceramic carrier, the carrier having wirings on one or both sides, or having embedded wirings). In either case, the chip is then integrated into other chips, discrete circuit elements, and / or other signal processing devices, such as (a) as part of an intermediate product such as a motherboard, or (b) Integrated. The end product can be any product, including toys and other low-end applications or integrated circuits used in high-end computer products with displays, keyboards or other input devices, and central processing units.

Like numbers refer to like or similar elements in the figures referred to from now on.

Referring first to Figures 3a and 3b, the channel response of a 20 mm long link in both the frequency domain (i. E., S21 parameters) and time domain is shown for carrier links 26 in Figure 2, respectively. Due to the series resistance, a significant DC attenuation (~ 6dB) occurs, and at 5GHz there is a loss of 17dB. In the time domain, the response to a solitary " 1 " bit at 10 gigabits per second shows a post-cursor ISI that extends over several bit periods. To compensate for this channel, the DFE requires many taps, but in high-density I / O environments the cost associated with power and chip area can be unrealistically high.

Looking closely at the time domain channel response, we can find a new solution for equalizing this high-resistance channel. The impulse response of the channel may well be modeled by decaying exponential at all times over a two unit interval (UI) since the main cursor. Since the impulse response of the primary RC low pass filter has an exponentially decreasing form, a filter in the DFE feedback path can be employed to generate the signal needed to remove the post-cursor ISI in the received data input. For example, a DFE with a primary RC low-pass feedback filter extends the data transfer rate of 10-mm on-chip interconnects to 2 gigabits per second. Because many of the many taps required for conventional DFE implementations have been replaced by simple RC filters, much power and chip area can be saved.

4, a continuous-time infinite impulse response (IIR) filter 104 having a frequency-domain transfer function G (s) is provided in the DFE feedback path 108 of the DFE circuit 100. The summation amplifiers 106 add on feedback from path 108 to the data input. If the primary RC low-pass filter can not get close to the channel response, the higher-order filter will be able to better remove the ISI.

In many channels, if both conventional individual taps (e.g., H1, H2) and IIR filter 204 are placed in feedback paths 208 of DFE 200, as in FIG. 5, It will be well removed. The first two taps of the discrete taps (e.g., H1 and H2 ... H _n ) of the post-cursor in the rapidly changing region of the channel impulse response immediately following the main cursor (Irrespective of the IIR filter 204) since these early post-cursors are often followed by (and followed by later post-cursors) ) Does not fall along an exponentially decreasing curve. In fact, the impulse response of the 20 mm silicon carrier channel shown in Figure 3b is an example of this point, in which the first post cursor (denoted H1) is a curve denoted H2e- ^{t /} And it does not drop exactly along the time constant of the decreasing function. Therefore, to correctly equalize such a silicon carrier link, a DFE 200 with a separate first tap H1 may be employed, wherein the individual first tap compensates the remainder of the post-cursors of the channel response Lt; RTI ID = 0.0 > IIR < / RTI >

The DFE 200 with IIR filter 204, including the silicon carrier link example of FIG. 2, has a chip area-efficiency and power-efficient structure for equalizing many channels, but full- It may not be suitable for extending to a high data transmission rate. At data transfer rates approaching the limits of technology (e.g., 10 gigabits per second in current CMOS technology), half-rate DFE structures are known to be more power-efficient than full-rate structures. However, it is very difficult to implement a half-rate DFE in an IIR filter because there is no full-rate regenerated signal available to drive the input of the IIR filter.

In FIG. 6, a half-rate DFE 300 according to an exemplary embodiment is shown. The half-rate DFE 300 naturally translates the input data into two parallel data streams 302 (specifically, even data bits D _E , and odd data bits D _o ) Demultiplex. Only one of the half-rate data streams is fed back to the IIR filter 304 to obtain the desired response because the impulse response of the IIR filter 304 is not just odd data bits or odd data bits , And to convolve into a complete bit sequence. As described above, obtaining a signal suitable for driving the input of the IIR filter 304 is a challenge when using a half-rate implementation. Half-rate structure 300 provides power-efficient and area-efficient means to obtain such signals.

)로 구동된다. 그리하여, 상부(top) 슬라이서(306)는 이븐(even) 데이터 비트들(D_E)을 생산하고, 하부 (bottom) 슬라이서(306)는 오드(odd) 데이터 비트들(D_O)을 생산한다. 슬라이서들(306) 앞에 위치한 합산기들(312)은 DFE 궤환 신호들을 수신된 데이터 입력에 합산하는데 사용된다. 제1 DFE 궤환 탭(H1)은 종래의 개별 타입(discrete type)이고, 또한 채널 임펄스 응답의 제1 포스트 커서와 정합되도록 독립적으로 조절될 수 있다. 하프-레이트 구조에서, 이전(previous) 데이터 비트는 DFE 반쪽의 반대 구조(the opposite DEF half)에 의해 결정되고, 따라서 이븐 데이터 경로를 위한 H1 탭(H1_E로 표시됨)은 오드 데이터 비트들로부터 궤환되고, 오드 데이터 경로를 위한 H1 탭(H1o로 표시됨)은 이븐 데이터 비트들로부터 궤환된다. 채널 임펄스 응답의 포스트 커서들 중 나머지로 인한 ISI는 IIR 필터(304)의 출력인 V_IIR에 의해 보상된다. Two pseudo-decision slicers (or latches) 306 driven by the half-rate clock CLK are used to sample the data input. The slicers 306 are coupled to the clocks CLK < RTI ID = 0.0 > and /

. Thus, the top slicer 306 produces even data bits D _E and the bottom slicer 306 produces odd data bits D _o . Summers 312 located before the slicers 306 are used to sum the DFE feedback signals to the received data input. The first DFE feedback tap H1 is a conventional discrete type and can also be independently adjusted to match the first postcursor of the channel impulse response. In the half-rate structure, the previous data bit is determined by the opposite DEF half of the DFE, so that the H1 tap (denoted H1 _E ) for the even data path is fed back from the odd data bits And the H1 tap (indicated by H1o) for the odd data path is fed back from the even data bits. The ISI due to the rest of the post-cursors of the channel impulse response is compensated by V _IIR , which is the output of IIR filter 304.

To reliably remove the ISI, the impulse response of the IIR filter 304 needs to be convolved with the complete bit sequence of the data input. To achieve this, a 2: 1 multiplexer (MUX) 310 with a selector driven by the CLK is employed, which forms the full-rate data D _FR suitable for driving the input of the IIR filter 304 The even and odd data bits D _{E O,} and D) is to interleaving (interleave) a.

In the timing diagram of Figure 7, the phase of the CLK is controlled by a clock and data recovery (CDR) circuit or some other device by which the input data bits are applied to the child's And sampled at the center of the eye. If the CLK signal phase driving the select function of the MUX is selected, as shown in FIG. 7, D _FR is delayed by 1 (one) UI relative to the first of the D _E and D _O bits . Because of this 1 UI delay, the earliest post cursor compensated by the IIR filter output (V _IIR ) is the second one (corresponding to the H2 tap in the conventional multi-tap DFE).

The embodiment of FIG. 6 shows a way to make the IIR filter 304 in addition to the half-rate DFE structure chip area-efficient and power-efficient, with the only overhead in this circuit (of course, the IIR filter 304 ) Is a 2: 1 MUX 310 used to form full-rate data. This small overhead can also be reduced to negligible levels when the 2: 1 MUX 310 and IIR filter 304 functions are combined into a single circuit.

8 illustrates an example of a combined circuit implementation in a 2: 1 MUX 410 and IIR filter 404 within a single current mode logic (CML) Fig. Since the circuit 400 is a fully differential circuit, the differential output magnitude of this circuit is proportional to the difference between the two tail current sources 406 and 408, I _D. The common-mode current I _CM and the resistance R _CM are set to obtain the desired common-mode output level from the IIR filter 404. Although I _D can be used to scale the magnitude of the differential output signal, the resistance R _D And the RC time constant of the IIR filter 404 can also be adjusted by adjusting the capacitance C _D (e.g., switched resistors and switched capacitors). In the combined MUX / IIR filter circuit 400, the only signal that represents only full-rate data is the net current delivered to the RC load.

및

)은, 임피던스 터미네이션을 위한 전압 V_TERM에 접속된 저항들(R_IN)을 갖는다. DFE 궤환 신호 H1에 의해 스위치 된 차동 쌍의 테일 전류는, ISI의 제1 포스터 커서를 보상하는데 필요한 탭 가중 계수를 세트(set)시키기 위해 조절된다. V_OS에 의해 스위치된 차동 쌍은, 디바이스 부정합으로 인한 정적 오프셋(static offset)을 보상하기 위해 DC 전류를 제공한다. 합산된 전류들은 부하 저항들 R_L1에 의해 전압으로 변환된다. 합산기(456)의 출력 전압들(

및

)은, 본 명세서에서 표준 CML 래치로 구현되는, 의사 결정 슬라이서(458)에 의해 샘플된다. Within the structure of FIG. 6, the summing amplifiers 312 and decision slicers 306 may be implemented with conventional circuit techniques. By way of example, FIG. 9 shows how the devices can be implemented as CML circuits. Referring to FIG. 9, signal summation can be accomplished in the current domain by connecting ("dotting") the drains of the multiple differential pairs of transistors (or collectors if implemented with bipolar technology) to each other. The differential pairs receiving the data input (D _in ) and the output of the IIR filter (V _IIR ) cause the voltage to be resistively changed using resistors 452 to more linearly convert the voltage into current (resistive degenerated). A resistive degeneration is not employed in the other differential pairs used as the current switches 454. Data inputs (

And

_Has resistors R _IN connected to a voltage V _TERM for impedance termination. The tail current of the differential pair switched by the DFE feedback signal H1 is adjusted to set the tap weighting factor necessary to compensate the first poster cursor of the ISI. The differential pair switch by V _OS, the device is due to the mismatch provides a DC current in order to compensate for the static offset (static offset). The summed currents are converted to voltages by load resistors R _L1 . The output voltages of the summer 456 (

And

) Are sampled by a decision slicer 458, which is implemented herein as a standard CML latch.

In Figure 9, the cascaded DFE summing amplifier 456 and decision slicer 458 are conventional techniques that, unless significant power is used, cause a significant delay in the critical path 460 of the DFE Respectively. In order to achieve reliable operation, the feedback signals of the DFE are required to be correctly established at the slicer input before the next data is determined. The critical path 460 of the DFE, indicated by dashed lines in FIG. 9, is the H1 feedback loop, and the delay of the H1 feedback loop is one (1) UI or less. The RC time constant at the output of the summing amplifier 456 can add significant delay to this critical path 460 by degrading the settling time of the feedback signals. To reduce the RC time constant so that the critical timing requirements can be satisfied, the load resistance R _L1 must often be reduced to a low value. In order to meet the amplification gain and voltage swing requirements, a reduction in R _L1 must take place proportional to the amount of increase in operating currents, which leads to high power consumption. The input stage of the data slicer 458 includes resistive loads R _L2 .

10, a schematic diagram illustrating a combined slicer and summer circuit 500 in accordance with one embodiment is shown. A more power-efficient approach to meeting the critical timing requirements is to eliminate the RC delay by injecting the summer output current directly into a resettable current-comparator PMOS load operating as a slicer 502. [ If CLK is high (the high combination is low), PMOS reset transistors 506 pull the output nodes to a positive power supply. When CLK goes low (the complement of the row goes high), the summer output currents cause the parasitic capacitors on the nodes to discharge to a low voltage. Depending on the sign of the summed differential currents, one of the positive or negative differential voltages begins to occur. When the common-mode output falls sufficiently low, the cross-connected PMOS transistors 507 in the slicer 502 are turned on to provide regeneration gain, and as a result (depending on the polarity of the differential voltage ) Latches a binary number 0 or 1. Eliminating the RC delay between the summation and latching functions makes it easier to meet timing constraint conditions of the DFE critical path, thereby enabling the desired data rate to be achieved with low power consumption. By combining these functions into a single circuit stage, the chip area can also be saved.

Some of the schematic examples shown in FIG. 10 improve DFE performance. For example, the pass gate sample-and-holds 508, which receive the D _IN input signal and are switched by CLK, may be used to provide the input during the valuation phase, And is used to hold a linear transconductor constant, which may be relatively long with small input overdrive levels. This holding of the input signal reduces the frequency-dependent loss of the receiver. In Figure 9, as in the CML summing amplifier, D _IN is the change of the resistance (resistive degeneration) And V _IIR are used to improve linearity in converting to current.

11 is shown according to another embodiment, wherein the half-rate structure 600 of the DFE with IIR filter 604 in this embodiment employs a combined sum / dispersion circuit 500. In order to maintain the valid values of D _E and D _O during both phases of CLK, the combined summing / distributing circuit 500 does not maintain the valid data output bits during reset, (slave latches) 602 are placed at the outputs of the summer / slicer circuits 500. Each slave latch 602 is in an opaque (or closed) state while the corresponding summing / slicer circuit 500 is reset, but the corresponding summing / slicer circuit 500 is evaluating ), The slave latch is switched to the transparent (or open) state. Therefore, the slave latches 602 add only a small propagation delay to the D _E and D _O data outputs.

The principles of the embodiment shown in FIG. 10 are applicable to multi-tap DFEs as well as DFEs with IIR filters. That is, combining summers and slicers has utility independent of using IIR filters in DFEs. For example, if the differential pair receiving the output of the IIR filter (V _IIR ) 604 is replaced by a differential current switch controlled by the DFE feedback signal H2 (similar to that shown for H1) A combined summing / slicer circuit 500 suitable for use in a two-tap DFE can be obtained. If a DFE with more than two taps is desired, the combined summing / slicer circuit 500 can be modified by adding more differential pairs to the current summer 504. [ The application of the combined summing / slicer circuit 500 can be used to implement conventional multi-tap DFEs while achieving a useful reduction in power and chip area. This is because eliminating the RC delay between the summing and latching functions makes it easier to satisfy the critical timing constraints of all DFEs.

A number of standard latch designs can be used to implement the slave latches 602 shown in FIG. 11, including CML and static CMOS types. However, these types of standard latches may have deficiencies in the application. For example, CML latches are usually considered to be the fastest available type, but because of their high static power consumption, they do not match the design purpose of a power-efficient DFE, which is one motivation behind the consideration of a DFE with an IIR filter. Static CMOS latches are more power-efficient, but their low speed can increase the delay in the critical path, and as a result the maximum operating frequency of the DFE is degraded.

Figure 12 shows a schematic view of a latching structure 700. Latching structure 700 has two differential regenerate stages 702 and 704 cascaded to achieve a higher speed and sensitivity than a static CMOS latch. In the exemplary embodiment shown in Figure 12, the input transistors of the first stage are NMOS devices 706 and the input transistors of the second stage are PMOS devices 708, but the device types change the basic operating principle You can do it the other way. When latch 700 is opaque, CLK remains high (its complement remains low). Thus, the PMOS switches 710 precharge the outputs of the first stage 702 to a positive power supply. Because the outputs of the first stage 702 are connected to the power supply, the PMOS input devices 708 of the second stage 704 are shut off so that the second stage is only stored previously The bit levels, i.e., their outputs, retain the previous bit decision. When CLK goes low (its complement goes high), the first stage 702 is turned on and begins to regenerate the input signal due to the cross-coupled PMOS transistors 711 in the load. At the same time, the common-mode output of the first stage is lowered, which causes the input transistors 708 of the second stage 704 to turn on. When the output of the first stage 702 is regenerated to a sufficiently high level, the logical state of the stage 704 is switched. Because the stage 704 (not receiving the clock signal) has NMOS transistors 712 cross-connected in its load, the output of the stage is amplified with further regeneration. Once the regeneration is complete and switching is complete, conduction through the transistors is interrupted, so this latch consumes only dynamic power, not static power. For this reason, the latch has more power-efficiency than the CML latch.

In one embodiment, the latch 700 is particularly useful when receiving a weakly regenerating signal from a component such as a summer / slicer 500 (Figure 11). In a particularly advantageous embodiment, the first stage 702 of the latch 700 is coupled to a previous stage 702 of a previous component (e.g., a summer / slicer) to allow the weaker playback input signal to be amplified by the first stage 702 (500)). This benefit can be ascertained by simulating a latch 700 with a summer / slicer 500 coupled.

When performing the simulation, the input signal to the summer / slicer 500 is very small, and its output is also weakly reproduced. The weak regeneration input signal transmitted to the latch 700 is amplified by regeneration of the first stage 702, but the input signal is rail-to-rail until the time CLK goes high (its complement is low) - It is not fully regenerated with rail-to-rail signal levels. With further playback, the output of the second stage 704 is further amplified to approach the rail-to-rail signal levels. These rail-to-rail output signals of the second stage cross each other at a common-mode above half the supply voltage, which allows them to be connected to all CML or CMOS logic circuits as well as NMOS differential It is also adapted to directly drive a current switch (such as, for example, realizing a H1 tap in Figs. 9 and 10).

The dual regeneration latches shown in Figure 12 are also applicable to systems that are not DFEs with IIR filters. As shown in Figure 1, conventional multi-tap DFEs include a number of latches, and the delays of these latches occupy a fraction of all critical timing paths in the DFE. Because of the excellent speed and sensitivity over other power-efficient latches (e.g., static CMOS latches), the dual regenerative latch 700 can be coupled to conventional DFE structures or other circuits, The operating frequency can be increased without increasing consumption. In addition, regenerative latch 700 can be a basic building block of many digital and mixed-signal systems. Since the speed and sensitivity of the latches often have a significant impact on overall system performance, a majority of these systems may benefit from the superior functional characteristics of dual regenerative latches 700. [

To demonstrate and evaluate the performance of the half-rate DFE with an IIR filter, a test chip was designed and fabricated with 65 nm bulk CMOS technology. When the combined summator / slicer 500 of FIG. 10 is employed, the particular DFE structure selected for the design is the structure shown in FIG. The 2: 1 MUX and IIR filters were combined in a single stage 400 as shown in FIG. 8, and the slave latches were implemented with the dual reproduction latches 700 of FIG. The equalization capacities of the DFE with IIR filters are 30 ", 40 < RTI ID = 0.0 >',< / RTI > on a Printed Circuit Board (PCB), with gentle frequency rolloff characteristics similar to those expected in silicon carrier links. '', And '50''traces. The frequency response (S21 data) for these channels is as shown in Fig. The bathtub curves in the lower half of the figure represent the measured BER as a function of the clock sampling position when the DFE equalizes the PRBS7 data at 10 gigabits per second. For a 50 '' trace, a DFE with an IIR filter produces a 45% horizontal eye opening at BER = 10 ^-9 , which operates error-free at the center of the eye and consumes only 6.8 mW of power . For comparison, a conventional two-tap DFE was implemented using the same basic components and power consumption levels as a DFE with an IIR filter.

Table 1 compares the measured horizontal eye opening of a DFE with an IIR filter and the eye opening of a conventional two-tap DFE for both the PRBS7 and PRBS31 data patterns at a data transfer rate of 10 gigabits per second. In all channels tested, the DFE with IIR filter was superior to the performance of the two-tap DFE and revealed the effect of the present invention.

[Table 1]

Other modifications and variations of the described embodiments, such as the use of a quarter-rate instead of a half-rate structure, will be apparent to those of ordinary skill in the art. These modifications and variations are not to be regarded as a departure from the spirit and scope of the invention.

Although preferred embodiments (shown for purposes of illustration, but not limited to) of circuits and methods for DFE with reduced chip area and reduced power consumption have been described, modifications and variations are possible, But may be made by one of ordinary skill in the art. It is therefore to be understood that changes may be made in the particular embodiments which are disclosed and that such changes are within the scope and spirit of the invention as set forth in the appended claims. Accordingly, the contents of the present invention are described in detail in detail as required by the Patent Act, and the claims to be protected by the patent are set forth in the appended claims.

Claims (15)

In a 1 / n rate decision feedback equalizer (DFE), n is a positive integer and the DFE is:
A plurality of branches; And
A feedback circuit,
Each branch,
A summer circuit configured to add a feedback signal to the received input;
And a latch circuit configured to receive an output of the summer circuit, wherein the latch circuit of each branch is driven at different phases of the clock signal to generate different partial bit sequences < RTI ID = 0.0 > Provide,
Said feedback circuit comprising:
A multiplexer configured to receive as input the different partial bit sequences from the latch circuit of each branch, the multiplexer having a clocked select input and having a full-rate bit sequence to multiplex the different partial bit sequences from the latch circuit of each branch in order to assemble the sequence; And
And a filter configured to remove intersymbol interference (ISI) for a received input using the output of the multiplexer, wherein the output of the filter is provided to the summer of each branch,
DFE. The method according to claim 1,
Further comprising: at least one additional latch circuit coupled to the latch circuit, each additional latch circuit having a feedback loop for providing a feedback tab to the summing circuit, Add to the input
DFE. 3. The method according to claim 1 or 2,
Wherein the latch circuit further comprises a slicer coupled to the summer circuit within a single stage
DFE. delete delete delete A method for decision feedback equalization, the method comprising:
Providing a 1 / n rate decision feedback equalization circuit having a plurality of branches, wherein n is a positive integer;
Summing a feedback signal from the one or more branches with the received input using a summer circuit;
Receiving the output of the summer circuit with a latch circuit, the latch circuit of each branch being driven at different phases of the clock signal to provide different partial bit sequences;
Feeding back the outputs of the latch circuit to a multiplexer that receives as input the different partial bit sequences from the latch circuit of each branch, the multiplexer assembling a full-rate bit sequence and to multiplex the different partial bit sequences from the latch circuit of each branch for assemble; And
(ISI) for the received input, using a continuous time infinite impulse response (IIR) filter having a frequency domain transfer function, the filter comprising an output of the multiplexer as an input And the output of the filter is provided to the summing circuit of each branch,
Way. 8. The method of claim 7,
And providing a feedback tab to said summer circuit to add said feedback tab from at least one additional latch circuit to said received input.
Way. 9. The method according to claim 7 or 8,
Wherein the latch circuit and the summer circuit are combined in a single stage and the method further comprises reproducing the output of the single stage using dual regeneration latches.
Way. 11. A combined slicer and summer circuit comprising:
Differential output lines connected to a plurality of differential currents to be summed; And
And a resetable current-comparator load directly coupled to the differential lines, wherein the current-comparator load receives the summed differential currents directly from the differential output lines, and in response to the sign of the summed differential currents, Wherein a positive or negative differential voltage is generated between the differential output lines to latch binary 0 or 1,
Combined slicer and summer circuit. 11. The method of claim 10,
Wherein the differential currents comprise at least one of an input signal produced by a linear transconductor and a tap signal and a filter signal provided by feedback of a decision feedback equalizer (DFE)
Combined slicer and summer circuit. 12. The method of claim 11,
Pass gate sample-and-hold circuit connected to a linear transconductor receiving an input signal switched by the CLK to hold the input signal in a linear transconductor constant during the valuation phase. sample-and-hold circuit,
Combined slicer and summer circuit. A dual reproduction latch, comprising:
Two cascaded differential reproduction latch stages 702 and 704 to achieve improved speed and sensitivity, the stages comprising:
A first stage 702 having a first type of first input transistors 706, a second type of cross-coupled load transistors 711 and a second type of reset transistors,
A second stage 704 having a second type of second input transistors 708 and a first type of cross-coupled load transistors 712, wherein the first stage is in an opaque state, That is, when the reset transistors precharge the outputs of the first stage to the power supply voltage, the second input transistors of the second stage shut to retain the outputs at the levels representing the previous stored bits. When the first stage is activated, the second type of cross-coupled load transistors of the first stage begin to regenerate the input signal, and at the same time, the common mode output of the first stage falls and the second Turns on the second input transistors of the stage and the second stage includes the cross-coupled load transistors of the first type such that the output of the first stage provides additional regeneration gain Is switched after reaching the ball threshold signal level,
Dual playback latch. delete delete

Images