"A Theory and Practice To Overcome 50-Ω Legacy in High-Speed Link Applications" Byungsub Kim,

IEEE International SoC Design Conference, 2017

"An Integrated Potentiostat" Puneet Kanwar Kaur , Sooeun Lee and Byungsub Kim,

IDEC SoC Congress Chip Design Contest, 2017

"A Coefficient-Error-Robust FFE TX with 230% Eye Variation Improvement Without Calibration in 65-nm CMOS Technology" Byungsub Kim,

IEEE CAS Society Korean Workshop on Circuits and Systems, 2017