Member

POSTECH BEVIL LAB

Researchers and Students

정순규

M.S-Ph.D. Combined Student

Education

Ph.D. student at POSTECH, Korea, EE (Mar. 2018-Feb. 2026) 

B.S. degree at POSTECH, Korea, EE (Mar. 2014-Feb.2018)  


Research Interest

Electronic design automation 

Publication

[1] S. Jeong, W. Choi, J. Choi, A. Biswas, and B. Kim, "A Self-Supervised Learning of a Foundation Model for Analog Layout Design Automation," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), pp. 1–11, 2025.


[2] S. Jeong et al., "A Layout-to-Generator Conversion Framework With Graphical User Interface for Visual Programming of Analog Layout Generators," IEEE Access, vol. 12, pp. 125942–125954, 2024.


[1] S. Han, S. Jeong, C. Kim, H.-J. Park, and B. Kim, "GUI-Enhanced Layout Generation of FFE SST TXs for Fast High-Speed Serial Link Design," in 2020 57th ACM/IEEE Design Automation Conference (DAC), July 2020.