한창윤
M.S.-Ph.D. Combined Student
- Education
Ph.D. student at POSTECH, Korea, EE (Mar. 2020-Present)
B.S. degree at POSTECH, Korea, EE (Mar. 2015-Feb.2020)
- Research Interest
High-Speed Links, Signal/Power Integrity, Interconnect Modelling, Computer-Aided Design (CAD)
- Publication
[1] Changyoon Han, Jaeyoung Seo, and Byungsub Kim, "A Reflection Self-Canceling Design Technique for Multidrop Memory Interfaces," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 12, no. 11, pp. 1816-1823, Nov. 2022, doi: 10.1109/TCPMT.2022.3225160.
[2] Changyoon Han, Jaeyoung Seo, and Byungsub Kim, "A 6Gb/s Transceiver Design with Phase-Difference Modulation Signaling for Multi-drop DRAM Interface," Journal of Integrated Circuits and Systems (JICAS), 2022, accepted for publication.
[3] Sooeun Lee, Jaeyoung Seo, Changyoon Han, Hong-June Park, Jae-Yoon Sim, and Byungsub Kim, "A DFE-Enhanced Phase-Difference Modulation Signaling for Multi-Drop Memory Interfaces," in IEEE Transactions on Circuits and Systems II (TCAS-II): Express Briefs, vol. 68, no. 6, pp.1862-1866, June 2021.