문창재
M.S.-Ph.D. Combined Student
- Education
Ph.D. student at POSTECH, Korea, EE (Mar. 2019-Present)
B.S. degree at POSTECH, Korea, EE (Mar. 2014-Feb.2019)
- Research Interest
- High-Speed Links, Signal/Power Integrity, Interconnect Modelling
- Publication
[1] Changjae Moon, Iksu Jang, Sungmin Lim, Yaejoon Huh, and Byungsub Kim, "3 x 16 Gb/s Compact Single-ended PAM4 Transmitters with Inverter-based Crosstalk Compensation for Memory Interfaces," IEEE Transactions on Circuits and System II: Express Briefs (TCAS II), 2024.
[2] Changjae Moon, Jaeyoung Seo, Myungguk Lee, Iksu Jang, and Byungsub Kim, "A Single-Ended Inverter-based Addition-Only Feed-Forward Equalization Transmitter," IEEE Journal of Solid-State Circuit (JSSC), 2024.
[3] Myungguk Lee, Jaeik Cho, Junung Choi, Won Joon Choi, Jiyun Lee, Iksu Jang, Changjae Moon, Gain Kim, and Byungsub Kim, "Compact Single-ended Transceivers Demonstrating Flexible Generation of 1/N-rate Receiver Front-ends for Short-Reach Links," IEEE Transactions on Circuits and System I: Regular Papers (TCAS I), 2024.
[4] Jaeyoung Seo, Sooeun Lee, Myungguk Lee, Changjae Moon, and Byungsub Kim, "A 20-Gb/s/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links," IEEE Journal of Solid-State Circuit (JSSC), 2023.
[5] Iksu Jang, Jaeyoung Seo, Changjae Moon, and Byungsub Kim, "A Cost-efficient FPGA-based Embedded System for Biosensor Platform", IEEE International SoC Design Conference (ISOCC), 2022.
[6] Jaehyun Ko, Iksu Jang, Chanho Kim, Jihoon Park, Changjae Moon, Sooeun Lee, and Byungsub Kim, "A 50 Mb/s Full HBC TRX with Adaptive DFE and Variable-Interval 3x Oversampling CDR in 28nm CMOS Technology for A 75 cm Body Channel Moving at 0.75 Cycle/sec", IEEE 48th European Solid-State Circuits Conference (ESSCIRC), 2022.
[7] Changjae Moon, Jaeyoung Seo, Myungguk Lee, Iksu Jang, and Byungsub Kim, "A 20 Gb/s/pin 1.18 pJ/b 1149um2 Single-Ended Inverter-based 4-tap Addition-Only Feed-Forward Equalization Transmitter with Improved Robustness to Coefficient Errors in 28nm CMOS," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2022.
[8] Jaeyoung Seo, Sooeun Lee, Myungguk Lee, Changjae Moon, and Byungsub Kim, "A 20-Gb/s/pin 0.0024-mm2 Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error and Supply Noise for DCC/CDR-less Short-Reach Memory Interfaces," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2022.