"A Self-Supervised Learning of a Foundation Model for Analog Layout Design Automation" Sungyu Jeong, Won Joon Choi, Junung Choi, Anik Biswas, Byungsub Kim,

arXiv, 2025

"A Fast Design Optimization of On-Chip Equalizing Links Using Particle Swarm Optimization" Hyoseok Song, Kwangmin Kim, Gain Kim and Byungsub Kim,

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2024

"Review on Resistive Termination Techniques Driven by Wireline Channel Behaviors" Changjae Moon; Minsoo Choi; Myungguk Lee; Byungsub Kim,

IEEE Open Journal of the Solid-State Circuits Society, 2024

"An On-chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses" Won Joon Choi; Myungguk Lee; Junung Choi, Jaeik Cho; Gain Kim; Byungsub Kim,

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2024

"3 x 16 Gb/s Compact Single-ended PAM4 Transmitters with Inverter-based Crosstalk Compensation for Memory Interfaces" Changjae Moon; Iksu Jang; Sungmin Lim; Yaejoon Huh; Byungsub Kim,

IEEE Transactions on Circuits and Systems II: Express Briefs, 2024

"A Layout-to-Generator Conversion Framework with Graphical User Interface for Visual Programming of Analog Layout Generators" Sungyu Jeong; Chanhyong Lee; Minsu Kim; Iksu Jang; Myungguk Lee; Junung Choi; Byungsub Kim,

IEEE Access, 2024

"A Single-Ended Inverter-based Addition-Only Feed-Forward Equalization Transmitter" Changjae Moon; Jaeyoung Seo; Myungguk Lee; Iksu Jang; Byungsub Kim,

IEEE Journal of Solid-State Circuits, 2024

"Compact Single-ended Transceivers Demonstrating Flexible Generation of 1/N-rate Receiver Front-ends for Short-Reach Links" Myungguk Lee, Jaeik Cho, Junung Choi, Won Joon Choi, Jiyun Lee, Iksu Jang, Changjae Moon, Gain Kim, and Byungsub Kim,

IEEE Transactions on Circuits and Systems I : Regular Papers, 2024

"A 20-Gb/s/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links" Jaeyoung Seo; Sooeun Lee; Myungguk Lee; Changjae Moon; Byungsub Kim,

IEEE Journal of Solid-State Circuits, 2023

"A Speculative Divide-and-Conquer Optimization Method for Large Analog/Mixed-Signal Circuits: A High-Speed FFE SST Transmitter Example" Kwangmin Kim, Hyoseok Song, Byeongcheol Lee and Byungsub Kim,

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023

"A Reflection Self-Canceling Design Technique for Multidrop Memory Interfaces" Changyoon Han, Jaeyoung Seo, Byungsub Kim,

IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT), 2022

"A Compact Single-Ended Inverter-based Transceiver with Swing Improvement for Short-Reach Links" Myungguk Lee, Puneet Kanwar Kaur, Jaeyoung Seo, Seungho Han, and Byungsub Kim,

IEEE Transactions on Circuits and Systems I: Regular Papers, 2022

"A DFE-Enhanced Phase-Difference Modulation Signaling for Multi-Drop Memory Interfaces" Sooeun Lee, Jaeyoung Seo, Changyoon Han, Jae-Yoon Sim, Hong-June Park and Byungsub Kim,

IEEE Transactions on Circuits and Systems II: Express Briefs, 2021

"A 7.8 Gb/s 2.9 pJ/b Single-Ended Receiver With 20 tap DFE for Highly-Reflective Channels" Jaeyoung Seo, Jaehyun Ko, Kyunghyun Lim, Sooeun Lee, Jae-Yoon Sim, Hong-June Park and Byungsub Kim,

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020

"A 7.8 Gb/s/pin, 1.96 pJ/b Transceiver with Phase-Difference-Modulation Signaling for highly-Reflective Interconnects" Sooeun Lee, Jaeyoung Seo, Kyunghyun Lim, Jaehyun Ko, Jae-Yoon Sim, Hong-June Park and Byungsub Kim,

IEEE Transactions on Circuits and Systems I (TCAS-I), 2020